Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors
Hyunhyub Ko1,2,3,6,7, Kuniharu Takei1,2,3,6, Rehan Kapadia1,2,3,6, Steven Chuang1,2,3, Hui Fang1,2,3, Paul W. Leu1,2,3, Kartik Ganapathi1, Elena Plis5, Ha Sul Kim5, Szu-Ying Chen4, Morten Madsen1,2,3, Alexandra C. Ford1,2,3, Yu-Lun Chueh4, Sanjay Krishna5, Sayeef Salahuddin1 & Ali Javey1,2,3
- Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, USA
- Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720, USA
- Berkeley Sensor and Actuator Center, University of California, Berkeley, California 94720, USA
- Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan
- Electrical and Computer Engineering Department, and Center for High Technology Materials, University of New Mexico, Albuquerque, New Mexico 87106, USA
- These authors contributed equally to this work.
- Present address: School of Nanotechnology and Chemical Engineering, Ulsan National Institute of Science and Technology, Ulsan Metropolitan City, South Korea.
Correspondence to: Ali Javey1,2,3 Email: ajavey@eecs.berkeley.edu
Top of page
Abstract
Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance1, 2, 3, 4, 5, 6, 7, 8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied7, 9, 10: such devices combine the high mobility of III–V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored9, 11, 12, 13—but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO2 substrates. As a parallel with silicon-on-insulator (SOI) technology14, we use ‘XOI’ to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsOx layer (~1 nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6 mS µm−1 at a drain–source voltage of 0.5 V, with an on/off current ratio of greater than 10,000.
ftp://mail.ihim.uran.ru/localfiles/nature09541.pdf
